{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9697118","patent":{"patent_number":"US-9697118","title":"Memory controller with interleaving and arbitration scheme","assignee":null,"inventors":[],"filing_date":"2015-12-09T00:00:00.000Z","publication_date":"2017-07-04T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":18,"abstract":"A memory controller that implements an interleaving and arbitration scheme includes an address decoder that selects a memory bank for an access request based on a set of address least significant bits included in the access request. A core requiring sequential access to memory is routed to consecutive memory banks of the memory for consecutive access requests. When multiple cores request access to the same memory bank, an arbiter determines an access sequence for the cores. The arbiter can modify the access sequence without significantly increasing the complexity of the memory controller. The address decoder determines whether the selected memory banks are available and also whether an access request is a wide access request, in which case it selects two consecutive memory banks."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory controller with interleaving and arbitration scheme","description":"A memory controller that implements an interleaving and arbitration scheme includes an address decoder that selects a memory bank for an access request based on a set of address least significant bits","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9697118","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9697118","citation_suggestion":"Patentable. \"Memory controller with interleaving and arbitration scheme\" (US-9697118). https://patentable.app/patents/US-9697118","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9697118","json":"https://patentable.app/api/llm-context/US-9697118","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T10:32:29.537Z"}