{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9697306","patent":{"patent_number":"US-9697306","title":"Formal verification driven power modeling and design verification","assignee":null,"inventors":[],"filing_date":"2016-07-12T00:00:00.000Z","publication_date":"2017-07-04T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":1,"abstract":"A computer program product includes program instructions to: Receive a unit including register transfer level content for a component of an integrated circuit and one or more IP blocks; Select one or more input pins for each IP block; Assign a numerical value of either zero or one to each of the one or more input pins to yield at least one numerical sequence; For each numerical sequence, perform a check to yield a number of fails, wherein the check is formal verification of each of the one or more IP blocks; Determine a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails; Set the one or more input pins to the simulation condition for power modeling of the unit; and Determine a number of design errors of the unit based on the simulation condition."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Formal verification driven power modeling and design verification","description":"A computer program product includes program instructions to: Receive a unit including register transfer level content for a component of an integrated circuit and one or more IP blocks; Select one or ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9697306","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9697306","citation_suggestion":"Patentable. \"Formal verification driven power modeling and design verification\" (US-9697306). https://patentable.app/patents/US-9697306","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9697306","json":"https://patentable.app/api/llm-context/US-9697306","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T14:02:00.139Z"}