{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9697887","patent":{"patent_number":"US-9697887","title":"SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter","assignee":null,"inventors":[],"filing_date":"2015-10-15T00:00:00.000Z","publication_date":"2017-07-04T00:00:00.000Z","cpc_codes":["G11C","G06F","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":8,"abstract":"Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter","description":"Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the l","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9697887","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9697887","citation_suggestion":"Patentable. \"SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter\" (US-9697887). https://patentable.app/patents/US-9697887","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9697887","json":"https://patentable.app/api/llm-context/US-9697887","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T04:40:03.905Z"}