{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9703493","patent":{"patent_number":"US-9703493","title":"Single-stage arbiter/scheduler for a memory system comprising a volatile memory and a shared cache","assignee":null,"inventors":[],"filing_date":"2016-01-27T00:00:00.000Z","publication_date":"2017-07-11T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G11C"],"num_claims":30,"abstract":"Systems, methods, and computer programs are disclosed for scheduling memory transactions. An embodiment of a method comprises determining future memory state data of a dynamic random access memory (DRAM) for a predetermined number of future clock cycles. The DRAM is electrically coupled to a system on chip (SoC). Based on the future memory state data, one of a plurality of pending memory transactions is selected that speculatively optimizes DRAM efficiency. The selected memory transaction is sent to a shared cache controller. If the selected memory transaction results in a cache miss, the selected memory transaction is sent to a DRAM controller."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Single-stage arbiter/scheduler for a memory system comprising a volatile memory and a shared cache","description":"Systems, methods, and computer programs are disclosed for scheduling memory transactions. An embodiment of a method comprises determining future memory state data of a dynamic random access memory (DR","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9703493","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9703493","citation_suggestion":"Patentable. \"Single-stage arbiter/scheduler for a memory system comprising a volatile memory and a shared cache\" (US-9703493). https://patentable.app/patents/US-9703493","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9703493","json":"https://patentable.app/api/llm-context/US-9703493","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:27:33.257Z"}