{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9703708","patent":{"patent_number":"US-9703708","title":"System and method for thread scheduling on reconfigurable processor cores","assignee":null,"inventors":[],"filing_date":"2013-09-27T00:00:00.000Z","publication_date":"2017-07-11T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":18,"abstract":"Systems and methods for efficiently utilizing reconfigurable processor cores. An example processing system includes, for example, a control register comprising a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and dynamic core reallocation logic to temporarily merge a first processor core and a second processor core to speed execution of a first thread executed on the first processor core responsive to determining that a second thread executed on the second processor core has completed execution prior to a quantum associated with the second thread being reached and to determining that the inhibit bits indicate that the first and second cores may be merged."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"System and method for thread scheduling on reconfigurable processor cores","description":"Systems and methods for efficiently utilizing reconfigurable processor cores. An example processing system includes, for example, a control register comprising a plurality of inhibit bits, each inhibi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9703708","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9703708","citation_suggestion":"Patentable. \"System and method for thread scheduling on reconfigurable processor cores\" (US-9703708). https://patentable.app/patents/US-9703708","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9703708","json":"https://patentable.app/api/llm-context/US-9703708","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T04:55:06.430Z"}