{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9704569","patent":{"patent_number":"US-9704569","title":"One time programmable read-only memory (ROM) in SOI CMOS","assignee":null,"inventors":[],"filing_date":"2016-10-06T00:00:00.000Z","publication_date":"2017-07-11T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":15,"abstract":"A programmable read-only-memory (ROM) cell and method of operating. The ROM cell comprises: a silicon-on-insulator (SOI) substrate having a bottom substrate layer, an insulating layer formed over said bottom substrate layer, and a top semiconductor substrate layer. A series coupled CMOS NFET and PFET device is formed at said semiconductor substrate layer, each NFET and PFET device having a respective gate, drain and source terminals, wherein a source terminal of said PFET device is electrically shorted to a drain terminal of said NFET device. An injected charge storage layer is provided at an interface between a channel formed beneath a gate terminal of said PFET and the insulating layer. The charge storage layer having trapped charge carriers representative of a logic bit value. The stored bit value is physically undetectable data. Biasing conditions established at the substrate and PFET device enable injection of charge carriers into the charge storage layer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"One time programmable read-only memory (ROM) in SOI CMOS","description":"A programmable read-only-memory (ROM) cell and method of operating. The ROM cell comprises: a silicon-on-insulator (SOI) substrate having a bottom substrate layer, an insulating layer formed over said","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9704569","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9704569","citation_suggestion":"Patentable. \"One time programmable read-only memory (ROM) in SOI CMOS\" (US-9704569). https://patentable.app/patents/US-9704569","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9704569","json":"https://patentable.app/api/llm-context/US-9704569","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T03:40:21.027Z"}