{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9704573","patent":{"patent_number":"US-9704573","title":"Three-transistor resistive random access memory cells","assignee":null,"inventors":[],"filing_date":"2016-12-09T00:00:00.000Z","publication_date":"2017-07-11T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","H01L","G11C","G11C","G11C","G11C"],"num_claims":7,"abstract":"A pair of adjacent ReRAM cells in an array includes a first bit line for a row of the array, a second bit line for the row of the array, a p-channel word line associated with two adjacent columns in the array, and an n-channel word line associated with the two adjacent columns. A pair of ReRAM cells in the adjacent columns in the row each includes a switch node, a first ReRAM device connected between the first bit line and the source of a p-channel transistor. The drain of the p-channel transistor is connected to the switch node, and its gate is connected to the p-channel word line. A second ReRAM device is connected between the second bit line and the source of an n-channel transistor. The drain of the n-channel transistor is connected to the switch node, and its gate is connected to the n-channel word line."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Three-transistor resistive random access memory cells","description":"A pair of adjacent ReRAM cells in an array includes a first bit line for a row of the array, a second bit line for the row of the array, a p-channel word line associated with two adjacent columns in t","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9704573","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9704573","citation_suggestion":"Patentable. \"Three-transistor resistive random access memory cells\" (US-9704573). https://patentable.app/patents/US-9704573","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9704573","json":"https://patentable.app/api/llm-context/US-9704573","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:18:30.282Z"}