{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9704790","patent":{"patent_number":"US-9704790","title":"Method of fabricating a wafer level package","assignee":null,"inventors":[],"filing_date":"2016-03-14T00:00:00.000Z","publication_date":"2017-07-11T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":9,"abstract":"A semiconductor package includes a redistribution layer (RDL) interposer having a first side, a second side, opposite to the first side. The RDL interposer comprises a first passivation layer, at least one dielectric layer on the first passivation layer, a metal layer in the at least one dielectric layer, a second passivation layer on the at least one dielectric layer, and a plurality of ball pads in the first passivation layer. At least one semiconductor die is mounted on the first side of the RDL interposer. A solder mask covers a lower surface of the first passivation layer and exposes the plurality of ball pads through a plurality of openings in the solder mask. An under-bump mettalization (UBM) layer is disposed at a bottom of each of the plurality of openings. A solder bump or solder ball is disposed on the UBM layer in each of the plurality of openings."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method of fabricating a wafer level package","description":"A semiconductor package includes a redistribution layer (RDL) interposer having a first side, a second side, opposite to the first side. The RDL interposer comprises a first passivation layer, at leas","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9704790","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9704790","citation_suggestion":"Patentable. \"Method of fabricating a wafer level package\" (US-9704790). https://patentable.app/patents/US-9704790","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9704790","json":"https://patentable.app/api/llm-context/US-9704790","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T11:37:12.992Z"}