{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9704990","patent":{"patent_number":"US-9704990","title":"Vertical FET with strained channel","assignee":null,"inventors":[],"filing_date":"2016-09-19T00:00:00.000Z","publication_date":"2017-07-11T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L"],"num_claims":10,"abstract":"A transistor in an integrated circuit device is formed using fabrication processes that include techniques to create a strain in the channel material, thereby improving the performance of the transistor. In one or more embodiments, an initial transistor structure is formed including a substrate, a dummy fin, and a hard mask. The dummy fin structure is narrowed. A channel is epitaxially grown on the dummy fin structure to create a strain on the channel. A first gate stack is formed over the channel. The hard mask and dummy fin are removed. A second gate stack is formed over the channel. Excess material is removed from the second gate stack. The formation of the transistor is finalized using a variety of techniques."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Vertical FET with strained channel","description":"A transistor in an integrated circuit device is formed using fabrication processes that include techniques to create a strain in the channel material, thereby improving the performance of the transist","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9704990","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9704990","citation_suggestion":"Patentable. \"Vertical FET with strained channel\" (US-9704990). https://patentable.app/patents/US-9704990","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9704990","json":"https://patentable.app/api/llm-context/US-9704990","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:15:34.692Z"}