{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9710590","patent":{"patent_number":"US-9710590","title":"Estimation of chip floorplan activity distribution","assignee":null,"inventors":[],"filing_date":"2014-12-31T00:00:00.000Z","publication_date":"2017-07-18T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":9,"abstract":"Simulation or calculation to estimate activity per unit in a chip design, combined with estimation of the specific location or region in which the unit logic will be finally placed, provides for calculation of an estimation of the activity distribution within the floorplan. Activity distribution estimation can be performed with fine granularity (at a gate level), at coarse granularity (at a macro level), or at an intermediate granularity (at a network-on-chip unit level). The estimation is displayed, visually, to a user of a design tool. Furthermore, the estimation is used to make manual or automatic optimizations of the floorplan and the location and configuration of units within the floorplan."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Estimation of chip floorplan activity distribution","description":"Simulation or calculation to estimate activity per unit in a chip design, combined with estimation of the specific location or region in which the unit logic will be finally placed, provides for calcu","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9710590","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9710590","citation_suggestion":"Patentable. \"Estimation of chip floorplan activity distribution\" (US-9710590). https://patentable.app/patents/US-9710590","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9710590","json":"https://patentable.app/api/llm-context/US-9710590","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T12:48:30.278Z"}