{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9711228","patent":{"patent_number":"US-9711228","title":"Apparatus and methods of operating memory with erase de-bias","assignee":null,"inventors":[],"filing_date":"2016-05-27T00:00:00.000Z","publication_date":"2017-07-18T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C"],"num_claims":26,"abstract":"Methods of operating a memory include developing first and second voltage levels in first and second semiconductor materials, respectively, forming channel regions for first and second groupings of memory cells, respectively, of a string of series-connected memory cells during an erase operation while applying a third voltage level to control gates of the first grouping of memory cells and applying a fourth voltage level to control gates of the second grouping of memory cells. Apparatus include different groupings of memory cells of a string of series-connected memory cells adjacent respective portions of semiconductor material having a first conductivity type and separated from adjacent portions of semiconductor material having the first conductivity type by portions of semiconductor material having a second conductivity type, and a controller configured to apply respective and different voltage levels to control gates of memory cells of respective different groupings of memory cells during an erase operation."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Apparatus and methods of operating memory with erase de-bias","description":"Methods of operating a memory include developing first and second voltage levels in first and second semiconductor materials, respectively, forming channel regions for first and second groupings of me","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9711228","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9711228","citation_suggestion":"Patentable. \"Apparatus and methods of operating memory with erase de-bias\" (US-9711228). https://patentable.app/patents/US-9711228","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9711228","json":"https://patentable.app/api/llm-context/US-9711228","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:20:04.594Z"}