{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9711241","patent":{"patent_number":"US-9711241","title":"Method and apparatus for optimized memory test status detection and debug","assignee":null,"inventors":[],"filing_date":"2015-04-01T00:00:00.000Z","publication_date":"2017-07-18T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C"],"num_claims":18,"abstract":"Embodiments contained in the disclosure provide a method for memory built-in self-testing (MBIST). The method begins when a testing program is loaded, which may be from an MBIST controller. Once the testing program is loaded MBIST testing begins. During testing, memory failures are determined and written to a failure indicator register. The writing to the failure indicator register occurs in parallel with the ongoing MBIST testing. An apparatus is also provided. The apparatus includes a memory data read/write block, a memory register, a memory addressor, and a memory read/write controller. The apparatus communicates with the memories under test through a memory address and data bus."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and apparatus for optimized memory test status detection and debug","description":"Embodiments contained in the disclosure provide a method for memory built-in self-testing (MBIST). The method begins when a testing program is loaded, which may be from an MBIST controller. Once the t","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9711241","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9711241","citation_suggestion":"Patentable. \"Method and apparatus for optimized memory test status detection and debug\" (US-9711241). https://patentable.app/patents/US-9711241","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9711241","json":"https://patentable.app/api/llm-context/US-9711241","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T13:17:01.490Z"}