{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9711390","patent":{"patent_number":"US-9711390","title":"Shallow trench isolation trenches and methods for NAND memory","assignee":null,"inventors":[],"filing_date":"2015-05-21T00:00:00.000Z","publication_date":"2017-07-18T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":17,"abstract":"A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the substrate, forming a liner in the trench, wherein the liner includes a first dielectric material, adhering a halogen element to the liner, forming a second dielectric material in the trench, annealing the first dielectric material and the second dielectric material, exposing a portion of a surface of the second dielectric material, and isotropically etching the exposed portion of the surface of the second dielectric material to form an air gap in the shallow trench isolation trench."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Shallow trench isolation trenches and methods for NAND memory","description":"A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the substrate, forming a liner in the trench, where","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9711390","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9711390","citation_suggestion":"Patentable. \"Shallow trench isolation trenches and methods for NAND memory\" (US-9711390). https://patentable.app/patents/US-9711390","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9711390","json":"https://patentable.app/api/llm-context/US-9711390","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T04:31:12.694Z"}