{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9711530","patent":{"patent_number":"US-9711530","title":"Locally-trap-characteristic-enhanced charge trap layer for three-dimensional memory structures","assignee":null,"inventors":[],"filing_date":"2016-05-19T00:00:00.000Z","publication_date":"2017-07-18T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L"],"num_claims":14,"abstract":"Threshold voltage shift due to programming of a neighboring memory element can be reduced or suppressed by forming a compositionally modulated charge storage layer in a three-dimensional memory device. The compositionally modulated charge storage layer can be formed by providing an oxygen-containing dielectric silicon compound layer outside a tunneling dielectric layer, and subsequently nitriding portions of the oxygen-containing dielectric silicon compound layer only at levels of the control gate electrodes. An alternating stack of sacrificial material layers and insulating layers can be employed to form a memory stack structure therethrough. After removal of the sacrificial material layers, a nitridation process can be performed to convert physically exposed portions of the oxygen-containing dielectric silicon compound layer into silicon nitride portions, which are vertically spaced from one another by remaining oxygen-containing dielectric silicon compound portions that have inferior charge trapping property to the silicon nitride portions."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Locally-trap-characteristic-enhanced charge trap layer for three-dimensional memory structures","description":"Threshold voltage shift due to programming of a neighboring memory element can be reduced or suppressed by forming a compositionally modulated charge storage layer in a three-dimensional memory device","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9711530","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9711530","citation_suggestion":"Patentable. \"Locally-trap-characteristic-enhanced charge trap layer for three-dimensional memory structures\" (US-9711530). https://patentable.app/patents/US-9711530","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9711530","json":"https://patentable.app/api/llm-context/US-9711530","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T03:53:57.202Z"}