{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9711619","patent":{"patent_number":"US-9711619","title":"Stress memorization and defect suppression techniques for NMOS transistor devices","assignee":null,"inventors":[],"filing_date":"2016-01-19T00:00:00.000Z","publication_date":"2017-07-18T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":5,"abstract":"In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Stress memorization and defect suppression techniques for NMOS transistor devices","description":"In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9711619","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9711619","citation_suggestion":"Patentable. \"Stress memorization and defect suppression techniques for NMOS transistor devices\" (US-9711619). https://patentable.app/patents/US-9711619","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9711619","json":"https://patentable.app/api/llm-context/US-9711619","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T11:23:10.980Z"}