{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9715270","patent":{"patent_number":"US-9715270","title":"Power reduction in a parallel data communications interface using clock resynchronization","assignee":null,"inventors":[],"filing_date":"2016-02-10T00:00:00.000Z","publication_date":"2017-07-25T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","H04L","H04W","H04W"],"num_claims":16,"abstract":"A digital data communications mechanism includes multiple parallel lines, in which components of one or more lines are temporarily powered down to save power. Preferably, both the transmitter and receiver contain respective generators generating identical pre-determined pseudo-random bit streams, which are initially synchronized and which remain powered up when the line is temporarily powered down. Upon re-powering the line, the transmitter transmits the locally generated bit stream, and the receiver compares the received bit stream with its internally generated bit stream to determine an amount of shift required for re-synchronization."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Power reduction in a parallel data communications interface using clock resynchronization","description":"A digital data communications mechanism includes multiple parallel lines, in which components of one or more lines are temporarily powered down to save power. Preferably, both the transmitter and rece","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9715270","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9715270","citation_suggestion":"Patentable. \"Power reduction in a parallel data communications interface using clock resynchronization\" (US-9715270). https://patentable.app/patents/US-9715270","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9715270","json":"https://patentable.app/api/llm-context/US-9715270","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:36:54.917Z"}