{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9716080","patent":{"patent_number":"US-9716080","title":"Thin fan-out multi-chip stacked package structure and manufacturing method thereof","assignee":null,"inventors":[],"filing_date":"2016-11-25T00:00:00.000Z","publication_date":"2017-07-25T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer is disposed on the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the dummy spacer are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and the surface of the dummy spacer but exposes the polished cross-sectional surfaces. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Thin fan-out multi-chip stacked package structure and manufacturing method thereof","description":"A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9716080","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9716080","citation_suggestion":"Patentable. \"Thin fan-out multi-chip stacked package structure and manufacturing method thereof\" (US-9716080). https://patentable.app/patents/US-9716080","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9716080","json":"https://patentable.app/api/llm-context/US-9716080","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:18:58.489Z"}