{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9716582","patent":{"patent_number":"US-9716582","title":"Deserialized dual-loop clock radio and data recovery circuit","assignee":null,"inventors":[],"filing_date":"2015-09-30T00:00:00.000Z","publication_date":"2017-07-25T00:00:00.000Z","cpc_codes":["H04L","H04L","H04L","H04L","H04L","H04L"],"num_claims":21,"abstract":"A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Deserialized dual-loop clock radio and data recovery circuit","description":"A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9716582","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9716582","citation_suggestion":"Patentable. \"Deserialized dual-loop clock radio and data recovery circuit\" (US-9716582). https://patentable.app/patents/US-9716582","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9716582","json":"https://patentable.app/api/llm-context/US-9716582","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:22:41.317Z"}