{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9720697","patent":{"patent_number":"US-9720697","title":"Mechanism for instruction set based thread execution on a plurality of instruction sequencers","assignee":null,"inventors":[],"filing_date":"2012-09-10T00:00:00.000Z","publication_date":"2017-08-01T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":18,"abstract":"In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Mechanism for instruction set based thread execution on a plurality of instruction sequencers","description":"In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequen","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9720697","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9720697","citation_suggestion":"Patentable. \"Mechanism for instruction set based thread execution on a plurality of instruction sequencers\" (US-9720697). https://patentable.app/patents/US-9720697","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9720697","json":"https://patentable.app/api/llm-context/US-9720697","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T19:26:35.615Z"}