{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9721050","patent":{"patent_number":"US-9721050","title":"Structure for reducing pre-charge voltage for static random-access memory arrays","assignee":null,"inventors":[],"filing_date":"2016-05-16T00:00:00.000Z","publication_date":"2017-08-01T00:00:00.000Z","cpc_codes":["G11C","G06F","G06F","G11C","G11C","H01L","G11C","G11C","G11C"],"num_claims":14,"abstract":"A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Structure for reducing pre-charge voltage for static random-access memory arrays","description":"A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-li","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9721050","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9721050","citation_suggestion":"Patentable. \"Structure for reducing pre-charge voltage for static random-access memory arrays\" (US-9721050). https://patentable.app/patents/US-9721050","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9721050","json":"https://patentable.app/api/llm-context/US-9721050","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:24:54.979Z"}