{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9721053","patent":{"patent_number":"US-9721053","title":"Method and system for printed circuit board layout","assignee":null,"inventors":[],"filing_date":"2016-03-23T00:00:00.000Z","publication_date":"2017-08-01T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":10,"abstract":"A system for printed circuit board layout includes a processing unit and a memory unit. The memory unit stores physical node data and virtual node data. The processing unit is electrically coupled to the memory unit and configured to execute steps of a method for printed circuit board layout. In particular, the physical node data of a printed circuit board (PCB) is acquired. The physical node data include a plurality of data structure and coordinate points of the physical nodes. The virtual node data of the PCB is acquired. The virtual node data include a plurality of data structure of the virtual nodes. A corresponding relation of the physical nodes and the virtual nodes is determined according to the physical node data and the virtual node data. The virtual nodes are disposed at the physical node coordinate points according to the corresponding relation."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and system for printed circuit board layout","description":"A system for printed circuit board layout includes a processing unit and a memory unit. The memory unit stores physical node data and virtual node data. The processing unit is electrically coupled to ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9721053","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9721053","citation_suggestion":"Patentable. \"Method and system for printed circuit board layout\" (US-9721053). https://patentable.app/patents/US-9721053","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9721053","json":"https://patentable.app/api/llm-context/US-9721053","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T11:20:46.907Z"}