{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9721675","patent":{"patent_number":"US-9721675","title":"Memory device having input circuit and operating method of same","assignee":null,"inventors":[],"filing_date":"2016-11-09T00:00:00.000Z","publication_date":"2017-08-01T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":15,"abstract":"An input circuit of a memory device includes an input receiver to receive an input signal, a clock receiver to receive a clock signal, a data latch, an input signal delay path coupled to the input receiver and configured to provide a delayed internal input signal to the data latch, a first clock signal delay path coupled to the clock receiver and configured to provide a first delayed internal clock signal, a second clock signal delay path coupled to the input receiver and configured to provide a second delayed internal clock signal, and a multiplexer coupled to receive and select one of the first delayed internal clock signal and the second delayed internal clock signal in response to a test mode control signal, and to provide the selected signal to the data latch."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory device having input circuit and operating method of same","description":"An input circuit of a memory device includes an input receiver to receive an input signal, a clock receiver to receive a clock signal, a data latch, an input signal delay path coupled to the input rec","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9721675","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9721675","citation_suggestion":"Patentable. \"Memory device having input circuit and operating method of same\" (US-9721675). https://patentable.app/patents/US-9721675","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9721675","json":"https://patentable.app/api/llm-context/US-9721675","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T10:21:46.828Z"}