{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9721799","patent":{"patent_number":"US-9721799","title":"Semiconductor package with reduced via hole width and reduced pad patch and manufacturing method thereof","assignee":null,"inventors":[],"filing_date":"2014-11-07T00:00:00.000Z","publication_date":"2017-08-01T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":19,"abstract":"The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a dielectric layer, a component, and a first patterned conductive layer. The encapsulation layer has a first surface. The component is within the encapsulation layer and has a front surface and a plurality of pads on the front surface. The dielectric layer is on the first surface of the encapsulation layer, and defines a plurality of via holes; wherein the plurality of pads of the component are against the dielectric layer; and wherein the dielectric layer has a second surface opposite the first surface of the encapsulation layer. Each of plurality of via holes extends from the second surface of the dielectric layer to a respective one of the plurality of the pads. The first patterned conductive layer is within the dielectric layer and surrounds the via holes."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor package with reduced via hole width and reduced pad patch and manufacturing method thereof","description":"The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a dielectric layer, a component, and a first pattern","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9721799","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9721799","citation_suggestion":"Patentable. \"Semiconductor package with reduced via hole width and reduced pad patch and manufacturing method thereof\" (US-9721799). https://patentable.app/patents/US-9721799","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9721799","json":"https://patentable.app/api/llm-context/US-9721799","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:21:54.047Z"}