{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9721827","patent":{"patent_number":"US-9721827","title":"Semiconductor arrangement with stress control and method of making","assignee":null,"inventors":[],"filing_date":"2014-02-27T00:00:00.000Z","publication_date":"2017-08-01T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":20,"abstract":"One or more semiconductor arrangements are provided. The semiconductor arrangements include a buried layer over a well, a dielectric layer over the buried layer, a first gate stack over the dielectric layer and a S/D region disposed proximate the first gate stack. The S/D region has a first tip proximity region that extends under the first gate stack. One or more methods of forming a semiconductor arrangement are also provided. The methods include forming a S/D recess in at least one of a dielectric layer, a buried layer or a well, wherein the S/D recess is proximate a first gate stack and has a first recess tip proximity region that extends under the first gate stack as a function of the buried layer, and forming a S/D region in the S/D recess such that the S/D region has a first tip proximity region that extends under the first gate stack."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor arrangement with stress control and method of making","description":"One or more semiconductor arrangements are provided. The semiconductor arrangements include a buried layer over a well, a dielectric layer over the buried layer, a first gate stack over the dielectric","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9721827","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9721827","citation_suggestion":"Patentable. \"Semiconductor arrangement with stress control and method of making\" (US-9721827). https://patentable.app/patents/US-9721827","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9721827","json":"https://patentable.app/api/llm-context/US-9721827","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:52:35.895Z"}