{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9721831","patent":{"patent_number":"US-9721831","title":"Method and apparatus for semiconductor planarization","assignee":null,"inventors":[],"filing_date":"2015-12-03T00:00:00.000Z","publication_date":"2017-08-01T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":20,"abstract":"A method includes forming a plurality of first semiconductor fins and a plurality of second semiconductor fins in a substrate, depositing a gate electrode layer over the substrate, wherein upper portions of the plurality of first semiconductor fins and the plurality of second semiconductor fins are embedded in the gate electrode layer, depositing a reverse film over the gate electrode layer and applying a chemical mechanical polish process to the reverse film and the gate electrode layer, wherein during the step of applying the chemical mechanical polish process, depositing a slurry between a polishing pad and the reverse film, and wherein a slurry selectivity ratio of the gate electrode layer to the reverse film is greater than 1."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and apparatus for semiconductor planarization","description":"A method includes forming a plurality of first semiconductor fins and a plurality of second semiconductor fins in a substrate, depositing a gate electrode layer over the substrate, wherein upper porti","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9721831","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9721831","citation_suggestion":"Patentable. \"Method and apparatus for semiconductor planarization\" (US-9721831). https://patentable.app/patents/US-9721831","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9721831","json":"https://patentable.app/api/llm-context/US-9721831","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:33:49.300Z"}