{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9721849","patent":{"patent_number":"US-9721849","title":"High performance isolated vertical bipolar junction transistor and method for forming in a CMOS integrated circuit","assignee":null,"inventors":[],"filing_date":"2016-09-02T00:00:00.000Z","publication_date":"2017-08-01T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":11,"abstract":"A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"High performance isolated vertical bipolar junction transistor and method for forming in a CMOS integrated circuit","description":"A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9721849","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9721849","citation_suggestion":"Patentable. \"High performance isolated vertical bipolar junction transistor and method for forming in a CMOS integrated circuit\" (US-9721849). https://patentable.app/patents/US-9721849","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9721849","json":"https://patentable.app/api/llm-context/US-9721849","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:20:54.603Z"}