{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9721856","patent":{"patent_number":"US-9721856","title":"Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage","assignee":null,"inventors":[],"filing_date":"2015-06-25T00:00:00.000Z","publication_date":"2017-08-01T00:00:00.000Z","cpc_codes":["H01L","G05B","H01L","H01L","G05B"],"num_claims":11,"abstract":"A method and system are provided for implementing resistive defect performance mitigation for integrated circuits. A test is generated for identifying resistive defects. A first self heating repair process is performed for repairing resistive defects. Testing is performed to identify a mitigated resistive defect and a functional integrated circuit. Responsive to identifying a resistive defect not being mitigated and a functional integrated circuit, a second repair process is performed, then testing is performed again."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage","description":"A method and system are provided for implementing resistive defect performance mitigation for integrated circuits. A test is generated for identifying resistive defects. A first self heating repair pr","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9721856","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9721856","citation_suggestion":"Patentable. \"Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage\" (US-9721856). https://patentable.app/patents/US-9721856","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9721856","json":"https://patentable.app/api/llm-context/US-9721856","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:41:12.870Z"}