{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9727359","patent":{"patent_number":"US-9727359","title":"Virtual machine function based sub-page base address register access for peripheral component interconnect device assignment","assignee":null,"inventors":[],"filing_date":"2015-04-27T00:00:00.000Z","publication_date":"2017-08-08T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F"],"num_claims":20,"abstract":"A value stored in a guest device register is received from a virtual machine. A hypervisor generates a page table including a first mapping between the value stored in the guest device register and a first address of the host operating system and a second mapping between a second address of the guest operating system and a third address of a virtual machine function on the host operating system. The hypervisor modifies a first access status of the first mapping to include rendering memory of the host device referenced by the value stored in the guest device register accessible to the virtual machine function, and a second access status of the second mapping to include rendering the virtual machine function accessible to the virtual machine. The hypervisor initializes code on the virtual machine function to access the memory of the host device."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Virtual machine function based sub-page base address register access for peripheral component interconnect device assignment","description":"A value stored in a guest device register is received from a virtual machine. A hypervisor generates a page table including a first mapping between the value stored in the guest device register and a ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9727359","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9727359","citation_suggestion":"Patentable. \"Virtual machine function based sub-page base address register access for peripheral component interconnect device assignment\" (US-9727359). https://patentable.app/patents/US-9727359","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9727359","json":"https://patentable.app/api/llm-context/US-9727359","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T14:37:53.570Z"}