{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9734075","patent":{"patent_number":"US-9734075","title":"Cache memory control program, processor incorporating cache memory, and cache memory control method","assignee":null,"inventors":[],"filing_date":"2014-08-13T00:00:00.000Z","publication_date":"2017-08-15T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":18,"abstract":"A cache memory control procedure has: cache area allocating including allocating, in response to an acquisition request, and according to an effective cache usage degree that is based on a memory access frequency and a difference between a cache hit rate in a case where the dedicated cache area is allocated and a cache hit rate in a case where a shared cache area in the cache memory is allocated, the dedicated cache area for a higher effective cache usage degree and the shared cache area for a lower effective cache usage degree; and releasing the dedicated cache area which is allocated, in response to a release request which is issued during execution of a process by the processor and requests the release of the allocated dedicated cache area."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Cache memory control program, processor incorporating cache memory, and cache memory control method","description":"A cache memory control procedure has: cache area allocating including allocating, in response to an acquisition request, and according to an effective cache usage degree that is based on a memory acce","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9734075","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9734075","citation_suggestion":"Patentable. \"Cache memory control program, processor incorporating cache memory, and cache memory control method\" (US-9734075). https://patentable.app/patents/US-9734075","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9734075","json":"https://patentable.app/api/llm-context/US-9734075","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:20:54.867Z"}