{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9734896","patent":{"patent_number":"US-9734896","title":"Circuits and methods for performance optimization of SRAM memory","assignee":null,"inventors":[],"filing_date":"2016-06-30T00:00:00.000Z","publication_date":"2017-08-15T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":14,"abstract":"In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the SRAM circuit indicating that a series of SRAM cells along a selected row of SRAM cells will be accessed; a precharge first mode signal to the SRAM circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the SRAM circuit indicating that a last access along the selected row will occur. The SRAM circuit includes an array of SRAM cells arranged in rows and columns to store data. Each SRAM cell is coupled to: a corresponding word line along a row of SRAM cells; and a corresponding pair of complementary bit lines."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Circuits and methods for performance optimization of SRAM memory","description":"In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the SRAM circuit indicating that a seri","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9734896","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9734896","citation_suggestion":"Patentable. \"Circuits and methods for performance optimization of SRAM memory\" (US-9734896). https://patentable.app/patents/US-9734896","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9734896","json":"https://patentable.app/api/llm-context/US-9734896","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:49:00.526Z"}