{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9734920","patent":{"patent_number":"US-9734920","title":"Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memories","assignee":null,"inventors":[],"filing_date":"2015-09-28T00:00:00.000Z","publication_date":"2017-08-15T00:00:00.000Z","cpc_codes":["G11C","G11B","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":17,"abstract":"Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memories","description":"Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9734920","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9734920","citation_suggestion":"Patentable. \"Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memories\" (US-9734920). https://patentable.app/patents/US-9734920","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9734920","json":"https://patentable.app/api/llm-context/US-9734920","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T10:19:39.952Z"}