{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9735062","patent":{"patent_number":"US-9735062","title":"Defect reduction in channel silicon germanium on patterned silicon","assignee":null,"inventors":[],"filing_date":"2016-06-03T00:00:00.000Z","publication_date":"2017-08-15T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"After forming a blanket silicon germanium (SiGe) layer over a thinned silicon (Si) layer of a silicon-on-insulator (SOI) substrate, a portion of the SiGe layer located in an n-type FET (nFET) region of the SOI substrate is recessed, while masking another portion of the SiGe layer located in a p-type FET (pFET) region of the SOI substrate. The recessed portion of the SiGe layer in the nFET region is subsequently removed with an in-situ pre-clean etch. An epitaxial Si layer is re-grown in the nFET region over a portion of the thinned Si layer that is exposed by the removal of the recessed portion of the SiGe layer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Defect reduction in channel silicon germanium on patterned silicon","description":"After forming a blanket silicon germanium (SiGe) layer over a thinned silicon (Si) layer of a silicon-on-insulator (SOI) substrate, a portion of the SiGe layer located in an n-type FET (nFET) region o","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9735062","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9735062","citation_suggestion":"Patentable. \"Defect reduction in channel silicon germanium on patterned silicon\" (US-9735062). https://patentable.app/patents/US-9735062","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9735062","json":"https://patentable.app/api/llm-context/US-9735062","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:26:59.615Z"}