{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9735092","patent":{"patent_number":"US-9735092","title":"Manufacturing method of chip package structure","assignee":null,"inventors":[],"filing_date":"2016-06-20T00:00:00.000Z","publication_date":"2017-08-15T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":7,"abstract":"A manufacturing method of a chip package structure includes following steps. A substrate including a first metal layer, a second metal layer, and an insulation layer located between the first and the second metal layers is provided. A first groove is formed in the first metal layer to form a chip pad and bonding pads. The bonding pads are respectively located in recesses of the chip pad. A second groove is formed in the second metal layer to form a heat-dissipation block and terminal pads. The terminal pads are respectively located in recesses of the heat-dissipation block. Conductive vias are formed to connect the corresponding terminal pads and electrically connect the bonding pads with the terminal pads. A chip is disposed on the chip pad and electrically connected to the bonding pads. An encapsulant covering the chip is formed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Manufacturing method of chip package structure","description":"A manufacturing method of a chip package structure includes following steps. A substrate including a first metal layer, a second metal layer, and an insulation layer located between the first and the ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9735092","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9735092","citation_suggestion":"Patentable. \"Manufacturing method of chip package structure\" (US-9735092). https://patentable.app/patents/US-9735092","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9735092","json":"https://patentable.app/api/llm-context/US-9735092","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:17:43.422Z"}