{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9735094","patent":{"patent_number":"US-9735094","title":"Combined packaged power semiconductor device","assignee":null,"inventors":[],"filing_date":"2016-06-24T00:00:00.000Z","publication_date":"2017-08-15T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":6,"abstract":"A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Combined packaged power semiconductor device","description":"A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between b","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9735094","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9735094","citation_suggestion":"Patentable. \"Combined packaged power semiconductor device\" (US-9735094). https://patentable.app/patents/US-9735094","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9735094","json":"https://patentable.app/api/llm-context/US-9735094","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:05:02.739Z"}