{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9735128","patent":{"patent_number":"US-9735128","title":"Method for incorporating stress sensitive chip scale components into reconstructed wafer based modules","assignee":null,"inventors":[],"filing_date":"2014-02-11T00:00:00.000Z","publication_date":"2017-08-15T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":7,"abstract":"Techniques for constructing an electronic module are provided herein. For example, the techniques include orienting at least one die having a top side (e.g., a first side), a bottom side (e.g., a second side) and one or more side walls, on a substrate with the top side of the die proximate the substrate, coating the bottom side and each of the side walls of the die with a stress buffer material, forming a reconstructed wafer by encapsulating the coated die within a mold compound, and removing the substrate to expose the top side of the die."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for incorporating stress sensitive chip scale components into reconstructed wafer based modules","description":"Techniques for constructing an electronic module are provided herein. For example, the techniques include orienting at least one die having a top side (e.g., a first side), a bottom side (e.g., a seco","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9735128","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9735128","citation_suggestion":"Patentable. \"Method for incorporating stress sensitive chip scale components into reconstructed wafer based modules\" (US-9735128). https://patentable.app/patents/US-9735128","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9735128","json":"https://patentable.app/api/llm-context/US-9735128","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:59:11.102Z"}