{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9735256","patent":{"patent_number":"US-9735256","title":"Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features","assignee":null,"inventors":[],"filing_date":"2015-07-14T00:00:00.000Z","publication_date":"2017-08-15T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":20,"abstract":"A semiconductor device and method of forming the same are disclosed. The method includes receiving a substrate having an active fin, an oxide layer over the active fin, a dummy gate stack over the oxide layer, and a spacer feature over the oxide layer and on sidewalls of the dummy gate stack. The method further includes removing the dummy gate stack, resulting in a first trench; etching the oxide layer in the first trench, resulting in a cavity underneath the spacer feature; depositing a dielectric material in the first trench and in the cavity; and etching in the first trench so as to expose the active fin, leaving a first portion of the dielectric material in the cavity."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features","description":"A semiconductor device and method of forming the same are disclosed. The method includes receiving a substrate having an active fin, an oxide layer over the active fin, a dummy gate stack over the oxi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9735256","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9735256","citation_suggestion":"Patentable. \"Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features\" (US-9735256). https://patentable.app/patents/US-9735256","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9735256","json":"https://patentable.app/api/llm-context/US-9735256","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T04:57:01.303Z"}