{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9735988","patent":{"patent_number":"US-9735988","title":"High data rate multilevel clock recovery system","assignee":null,"inventors":[],"filing_date":"2016-12-12T00:00:00.000Z","publication_date":"2017-08-15T00:00:00.000Z","cpc_codes":["H04L","H04L","H04L","H04L","H04L","H04L","H04L","H04L","H04Q","H04Q"],"num_claims":20,"abstract":"Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"High data rate multilevel clock recovery system","description":"Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers m","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9735988","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9735988","citation_suggestion":"Patentable. \"High data rate multilevel clock recovery system\" (US-9735988). https://patentable.app/patents/US-9735988","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9735988","json":"https://patentable.app/api/llm-context/US-9735988","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T03:54:57.393Z"}