{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9740431","patent":{"patent_number":"US-9740431","title":"Memory controller and method for interleaving DRAM and MRAM accesses","assignee":null,"inventors":[],"filing_date":"2016-07-17T00:00:00.000Z","publication_date":"2017-08-22T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G06F","G06F","G11C","G11C"],"num_claims":20,"abstract":"A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory controller and method for interleaving DRAM and MRAM accesses","description":"A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9740431","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9740431","citation_suggestion":"Patentable. \"Memory controller and method for interleaving DRAM and MRAM accesses\" (US-9740431). https://patentable.app/patents/US-9740431","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9740431","json":"https://patentable.app/api/llm-context/US-9740431","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T03:56:55.153Z"}