{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9740807","patent":{"patent_number":"US-9740807","title":"Method to measure edge-rate timing penalty of digital integrated circuits","assignee":null,"inventors":[],"filing_date":"2015-01-29T00:00:00.000Z","publication_date":"2017-08-22T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":26,"abstract":"Methods for evaluating timing delays in unbalanced digital circuit elements and for correcting timing delays computed by static-timing models are described. Unbalanced circuit elements have large edge-rates at their input and small edge-rates at their output. Unbalanced circuit elements may be analyzed using a modified loaded ring oscillator. A statistical model and a fixed-corner model may be used to calculate timing delays associated with the unbalanced circuit elements and a timing delay error between the two models. The timing delay error may then be used to correct timing delays computed by static-timing models for similar unbalanced circuit elements within a more complex digital circuit."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method to measure edge-rate timing penalty of digital integrated circuits","description":"Methods for evaluating timing delays in unbalanced digital circuit elements and for correcting timing delays computed by static-timing models are described. Unbalanced circuit elements have large edge","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9740807","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9740807","citation_suggestion":"Patentable. \"Method to measure edge-rate timing penalty of digital integrated circuits\" (US-9740807). https://patentable.app/patents/US-9740807","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9740807","json":"https://patentable.app/api/llm-context/US-9740807","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:58:04.774Z"}