{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9741406","patent":{"patent_number":"US-9741406","title":"Semiconductor memory and memory system","assignee":null,"inventors":[],"filing_date":"2017-03-17T00:00:00.000Z","publication_date":"2017-08-22T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":7,"abstract":"A semiconductor memory, including: a plurality of data terminals for transmitting data; a plurality of buffer circuits, each being coupled to a corresponding one of the data terminals; and a control circuit receiving an access command, that controls reading data from a memory cell array or writing data to the memory cell array, and a terminal setting information issued with each access command, and controlling the buffer circuits based on the access command and the terminal setting information, wherein, when the terminal setting information indicates a first mode, all of the buffer circuits function as input buffer circuits or output buffer circuits based on the access command, and wherein, when the terminal setting information indicates a second mode, a part of the buffer circuits functions as the input buffer circuits and a remaining part of the buffer circuits functions as the output buffer circuits."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor memory and memory system","description":"A semiconductor memory, including: a plurality of data terminals for transmitting data; a plurality of buffer circuits, each being coupled to a corresponding one of the data terminals; and a control c","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9741406","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9741406","citation_suggestion":"Patentable. \"Semiconductor memory and memory system\" (US-9741406). https://patentable.app/patents/US-9741406","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9741406","json":"https://patentable.app/api/llm-context/US-9741406","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T14:25:21.930Z"}