{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9741659","patent":{"patent_number":"US-9741659","title":"Electrical connections for chip scale packaging","assignee":null,"inventors":[],"filing_date":"2015-12-28T00:00:00.000Z","publication_date":"2017-08-22T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a substrate, the substrate having a first direction of coefficient of thermal expansion mismatch. The semiconductor device includes a first opening through the post-passivation layer, the first opening comprising a plurality of elongated apertures. A longest of the plurality of elongated apertures comprises a first dimension, wherein the first dimension is aligned substantially perpendicular to the first direction of coefficient of thermal expansion mismatch."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Electrical connections for chip scale packaging","description":"Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a substrate, the substrate having a first direc","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9741659","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9741659","citation_suggestion":"Patentable. \"Electrical connections for chip scale packaging\" (US-9741659). https://patentable.app/patents/US-9741659","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9741659","json":"https://patentable.app/api/llm-context/US-9741659","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T11:21:55.398Z"}