{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9741769","patent":{"patent_number":"US-9741769","title":"Vertical memory structure with array interconnects and method for producing the same","assignee":null,"inventors":[],"filing_date":"2016-04-19T00:00:00.000Z","publication_date":"2017-08-22T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C"],"num_claims":14,"abstract":"Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers. A plurality of vias is formed through the vertical stack from the top layer to the bottom layer. A memory layer disposed adjacent the conductive layers in the vias. A selector device disposed adjacent the memory layer wherein the selector device comprises multiple layers of dissimilar metal oxides. A lateral electrical contact to the memory layer through the conductive layer. And a top contact electrically connected to the conductive layer through a portion of the memory layer and the portion of the memory layer wherein the portion of the memory layer is configured to store data therein."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Vertical memory structure with array interconnects and method for producing the same","description":"Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a b","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9741769","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9741769","citation_suggestion":"Patentable. \"Vertical memory structure with array interconnects and method for producing the same\" (US-9741769). https://patentable.app/patents/US-9741769","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9741769","json":"https://patentable.app/api/llm-context/US-9741769","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:22:49.546Z"}