{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9742280","patent":{"patent_number":"US-9742280","title":"Dynamic clock divide for current boosting","assignee":null,"inventors":[],"filing_date":"2016-06-07T00:00:00.000Z","publication_date":"2017-08-22T00:00:00.000Z","cpc_codes":["H02M","H02M","H02M","H02M","H02M"],"num_claims":17,"abstract":"In order to accelerate the response of buck converters to load transients buck converters having asymmetric phase designs having a load step detection are used. When a relatively large and fast load step is detected, the clock frequency of “fast”valley mode phases is reduced, which are populated with fast, low value inductors. The clock frequency is returned to its normal rate when the current in the “slow” phases has reached a suitable level."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Dynamic clock divide for current boosting","description":"In order to accelerate the response of buck converters to load transients buck converters having asymmetric phase designs having a load step detection are used. When a relatively large and fast load s","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9742280","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9742280","citation_suggestion":"Patentable. \"Dynamic clock divide for current boosting\" (US-9742280). https://patentable.app/patents/US-9742280","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9742280","json":"https://patentable.app/api/llm-context/US-9742280","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T11:19:00.797Z"}