{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9742603","patent":{"patent_number":"US-9742603","title":"Link training to recover asynchronous clock timing margin loss in parallel input/output interfaces","assignee":null,"inventors":[],"filing_date":"2016-11-29T00:00:00.000Z","publication_date":"2017-08-22T00:00:00.000Z","cpc_codes":["H04L","H04L"],"num_claims":24,"abstract":"In accordance with embodiments disclosed herein, there is provided systems and methods for link training between a host device and a device. The host device includes a clock source, front-end circuitry, a duty cycle monitor (DCM), link training logic, and a duty cycle adjustor (DCA). The front-end circuitry is to transmit a training sequence and a forward clock signal to the device and is to receive a strobe signal from the device over a physical transmission media. The DCM is to monitor duty cycle of the strobe signal and duty cycle of the clock signal. The link training logic is to determine a adjustment to the clock signal and is to generate a control signal. The DCA is to receive the clock signal and the control signal and is to adjust the clock signal to generate an adjusted forward clock signal in view of the control signal."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Link training to recover asynchronous clock timing margin loss in parallel input/output interfaces","description":"In accordance with embodiments disclosed herein, there is provided systems and methods for link training between a host device and a device. The host device includes a clock source, front-end circuitr","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9742603","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9742603","citation_suggestion":"Patentable. \"Link training to recover asynchronous clock timing margin loss in parallel input/output interfaces\" (US-9742603). https://patentable.app/patents/US-9742603","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9742603","json":"https://patentable.app/api/llm-context/US-9742603","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T16:30:55.096Z"}