{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9747041","patent":{"patent_number":"US-9747041","title":"Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device","assignee":null,"inventors":[],"filing_date":"2015-12-23T00:00:00.000Z","publication_date":"2017-08-29T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":25,"abstract":"Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device","description":"Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a targ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9747041","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9747041","citation_suggestion":"Patentable. \"Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device\" (US-9747041). https://patentable.app/patents/US-9747041","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9747041","json":"https://patentable.app/api/llm-context/US-9747041","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:02:01.032Z"}