{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9747109","patent":{"patent_number":"US-9747109","title":"Flexible instruction execution in a processor pipeline","assignee":null,"inventors":[],"filing_date":"2014-10-15T00:00:00.000Z","publication_date":"2017-08-29T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":20,"abstract":"Executing instructions in a processor includes analyzing operations to be performed by instructions, including: determining a latency associated with a first operation to be performed by a first instruction, determining a second operation to be performed by a second instruction, where a result of the second operation depends on a result of the first operation, and assigning a value to the second instruction corresponding to the determined latency associated with the first operation. One or more instructions are selected to be issued together in the same clock cycle of the processor from among instructions whose operations have been analyzed, the selected instructions occurring consecutively according to a program order. A start of execution of the second instruction is delayed by a particular number of clock cycles after the clock cycle in which the second instruction is issued according to the value assigned to the second instruction."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Flexible instruction execution in a processor pipeline","description":"Executing instructions in a processor includes analyzing operations to be performed by instructions, including: determining a latency associated with a first operation to be performed by a first instr","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9747109","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9747109","citation_suggestion":"Patentable. \"Flexible instruction execution in a processor pipeline\" (US-9747109). https://patentable.app/patents/US-9747109","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9747109","json":"https://patentable.app/api/llm-context/US-9747109","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T12:47:15.265Z"}