{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9747209","patent":{"patent_number":"US-9747209","title":"System and method for improved memory performance using cache level hashing","assignee":null,"inventors":[],"filing_date":"2016-02-26T00:00:00.000Z","publication_date":"2017-08-29T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":30,"abstract":"Various embodiments of methods and systems for cache-level memory management in a system on a chip (“SoC”) are disclosed. Memory utilization is optimized in certain embodiments through application of customized hashing algorithms at the lower level cache of individual application clients. Advantageously, for those application clients that do not require or benefit from hashing transaction traffic their transactions are not subjected to hashing. For those application clients that do benefit from hashing transaction traffic in order to minimize page conflicts at a double data rate (“DDR”) memory device, each client further benefits from a customized, and thus optimized, hashing algorithm. Because transaction streams arrive at the memory controller already hashed, or purposefully unhashed, the need for validating clients during a development phase is minimized."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"System and method for improved memory performance using cache level hashing","description":"Various embodiments of methods and systems for cache-level memory management in a system on a chip (“SoC”) are disclosed. Memory utilization is optimized in certain embodiments through application of ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9747209","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9747209","citation_suggestion":"Patentable. \"System and method for improved memory performance using cache level hashing\" (US-9747209). https://patentable.app/patents/US-9747209","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9747209","json":"https://patentable.app/api/llm-context/US-9747209","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:18:10.203Z"}