{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9747403","patent":{"patent_number":"US-9747403","title":"Power-and-ground (PG) network characterization and distributed PG network creation for hierarchical circuit designs","assignee":null,"inventors":[],"filing_date":"2015-07-13T00:00:00.000Z","publication_date":"2017-08-29T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":15,"abstract":"A chip layout can include a top-level portion and a set of blocks. The power-and-ground (PG) network for the chip layout can be specified by a set of chip-level PG constraints that is defined using a PG constraint definition language. The set of chip-level PG constraints can be characterized into new sets of PG constraints that correspond to smaller regions of the chip layout, e.g., a set of top-level PG constraints that corresponds to the top-level portion, and a set of block-level PG constraints for each block in the set of blocks. The new sets of PG constraints can then be provided to one or more instances of a PG compiler that executes on one or more processors to create the PG network for the chip layout."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Power-and-ground (PG) network characterization and distributed PG network creation for hierarchical circuit designs","description":"A chip layout can include a top-level portion and a set of blocks. The power-and-ground (PG) network for the chip layout can be specified by a set of chip-level PG constraints that is defined using a ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9747403","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9747403","citation_suggestion":"Patentable. \"Power-and-ground (PG) network characterization and distributed PG network creation for hierarchical circuit designs\" (US-9747403). https://patentable.app/patents/US-9747403","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9747403","json":"https://patentable.app/api/llm-context/US-9747403","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:46:45.166Z"}