{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9748200","patent":{"patent_number":"US-9748200","title":"Manufacturing method of wafer level package structure","assignee":null,"inventors":[],"filing_date":"2016-11-10T00:00:00.000Z","publication_date":"2017-08-29T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":6,"abstract":"A manufacturing method of a wafer level package structure includes the following steps. A chip is disposed on a supporting board, wherein the chip includes an active surface and a back surface opposite to the active surface, and a plurality of pads on the active surface, and the back surface of the chip is adhered to the supporting board through a die attach film (DAF). A molding is disposed on the supporting board to perform a wafer level exposed die molding procedure on the chip, wherein the molding surrounds the chip, and the pads of the chip are exposed out of the molding. A redistribution layer (RDL) is formed on the active surface of the chip, wherein the RDL is electrically connected to the pads. The supporting board and the DAF are removed from the chip."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Manufacturing method of wafer level package structure","description":"A manufacturing method of a wafer level package structure includes the following steps. A chip is disposed on a supporting board, wherein the chip includes an active surface and a back surface opposit","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9748200","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9748200","citation_suggestion":"Patentable. \"Manufacturing method of wafer level package structure\" (US-9748200). https://patentable.app/patents/US-9748200","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9748200","json":"https://patentable.app/api/llm-context/US-9748200","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:00:22.472Z"}