{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9748272","patent":{"patent_number":"US-9748272","title":"Semiconductor-on-insulator with back side strain inducing material","assignee":null,"inventors":[],"filing_date":"2012-04-21T00:00:00.000Z","publication_date":"2017-08-29T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":19,"abstract":"Embodiments of the present invention provide for the application of strain inducing layers to enhance the mobility of transistors formed on semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a strain inducing material is deposited on the excavated insulator region. The strain inducing material interacts with the pattern of excavated insulator such that a single layer provides both tensile and compressive stress to p-channel and n-channel transistors, respectively. In alternative embodiments, the entire substrate is removed before forming the strain inducing material."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor-on-insulator with back side strain inducing material","description":"Embodiments of the present invention provide for the application of strain inducing layers to enhance the mobility of transistors formed on semiconductor-on-insulator (SOI) structures. In one embodime","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9748272","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9748272","citation_suggestion":"Patentable. \"Semiconductor-on-insulator with back side strain inducing material\" (US-9748272). https://patentable.app/patents/US-9748272","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9748272","json":"https://patentable.app/api/llm-context/US-9748272","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:19:48.297Z"}